1 Answer Furthermore, these clock signals are particularly affected by technology scaling (see Moore's law), in that long global interconnect lines become significantly more resistive as line dimensions are decreased. This rapid and destructive phenomenon is known as the antenna effect. In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. If they express much more than this, they are usually considered to be a hardware description language such as Verilog, VHDL, or any one of several specific languages designed for input to simulators. The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. Helps you prepare job interviews and practice interview skills and techniques. These observations have lead to a power saving technique called clock gating, which involves adding logic gates to the clock distribution tree, so portions of the tree can be turned off when not needed. Question 1. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Sunday, October 31, 2010. Best IAS Coaching Institutes in Coimbatore. This check results a database which has all the mismatching geometries in both the layouts. Universal Verification Methodology (UVM) Interview Questions, Business administration Interview questions, Cheque Truncation System Interview Questions, Principles Of Service Marketing Management, Business Management For Financial Advisers, Challenge of Resume Preparation for Freshers, Have a Short and Attention Grabbing Resume. A power cycle is required to correct this situation. OurEducation is an Established trademark in Rating, Ranking and Reviewing Top 10 Education Institutes, Schools, Test Series, Courses, Coaching Institutes, and Colleges. In the case of a vacuum cleaner, these ports would be the three metal prongs in the plug. An Asic is a microchip designed for a special application such as a particular kind of transmission protocol or a hand-held computer. Your email address will not be published. Ques. SVA ( System verilog Assertion) 1. Functionality of .lib files will be taken from spice models and added as an attribute to the .lib file. Lets say you want to design an Adder with certain specification . UVM Interview Questions Below are the most frequently asked UVM Interview Questions, What is uvm_transaction, uvm_seq_item, uvm_object, uvm_component? Ques. If they are the same, LVS passes and the designer can continue. Resistor-capacitor transistor logic (RCTL), Emitter coupled logic (ECL) also known as Current-mode logic (CML), Transistor-transistor logic (TTL) and variants, P-type Metal Oxide Semiconductor logic (PMOS), N-type Metal Oxide Semiconductor logic (NMOS), Complementary Metal-Oxide Semiconductor logic (CMOS), Bipolar Complementary Metal-Oxide Semiconductor logic (BiCMOS). Interview Question related to UVM and OVM methodology with answers. Listed here in rough chronological order of introduction along with their usual abbreviations of Logic family: Question 11. The antenna effect, more formally plasma induced gate oxide damage, is an efffect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. Subscribe to: Post Comments (Atom) Categories. Here, the designer integrates radio frequency (RF) analog and base band digital circuitry on a single chip. So, candidates trace your path as Asic design engineer, Asic verification engineer, Asic Design RTL engineer, staff engineer, etc, by checking into the below listed Asic job interview questions and answers. What are difference between SVA and other assertions? Then log on to www.wisdomjobs.com. The word antenna is somewhat of a misnomer in this context—the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. Ques. Get the free PDF in your inbox * Send me the PDF. Instances have "ports". It then generates a netlist from each one and compares them. 1. draw a circuit to divide a clock by 2. XOR Check: This step involves comparing two layout databases/GDS by XOR operation of the layout geometries. Nets are the "wires" that connect things together in the circuit. Explain the 1k boundary concept in AHB? 187 asic design interview questions. Here, you may find the most frequently asked Interview Questions on SystemVerilog, UVM, Verilog, SoC . Instance based netlists usually provide a list of the instances used in a design. The push for reduced cost, more compact circuit boards, and added customer features has provided incentives for the inclusion of analog functions on primarily digital MOS integrated circuits (ICs) forming mixed-signal ICs. What is the size of the max data that can be transferred in a single transfer? ERC steps can also involve checks for unconnected inputs or shorted outputs. Well..the candidate gave answer: Low power design; Can you talk about low power techniques? How low power and latest 90nm/65nm technologies are related? LEts have a look at the different types of questions that can be asked over these small but most required circuit. Please don't mind. Backend (Physical Design) Interview Questions and Answers What is the difference between FPGA and ASIC? ASIC interview Question & Answer A blog to collect the interview questions and answer for ASIC related positions. Antenna Check: Antenna checks are used to limit the damage of the thin gate oxide during the manufacturing process due to charge accumulation on the interconnect layers (metal, polysilicon) during certain fabrication steps like Plasma etching, which creates highly ionized matter to etch. (c) FPGA design is slower than corresponding ASIC design. Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. Previously only logic synthesis had to satisfy timing requirements. What is the difference between `uvm_do and `uvm_ran_send? The threshold voltage of a MOSFET is affected by the voltage which is applied to the back contact. 8- Which Hardware description language is used for ASICs? If the connection to silicon does not exist, charges may build up on the interconnect to the point at which rapid discharge does take place and permanent physical damage results to thin transistor gate oxide. Questions about previous verification projects and internship experience. To save power, clock gating refers to adding additional logic to a circuit to prune the clock tree, thus disabling portions of the circuitry where flip flops do not change state. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. What Physical Timing Closure? Net-based netlists usually describe all the instances and their attributes, then describe each net, and say which port they are connected on each instance. Most basic question is draw digital gates using transistors, difference between bipolar and cmos, … It is not an academic exam, where text-book preparation might come handy. I have overall 6 years of experience in the Education Industry. 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